The present invention relates to technology for controlling access to DRAMs capable of burst transfers, for the purpose of, e.g., graphics processing.
In most of the current graphics processors, a dedicated video memory is not used, and instead a frame-buffer area is provided, together with other process data, in an SDRAM (synchronous DRAM) for cost reduction. In those graphics processors, to write graphic data into the frame-buffer area, the pixel positions and pixel data of the graphic data are calculated and the pixel data is written into the frame-buffer area in the SDRAM in accordance with the pixel positions. On the other hand, to display drawing data stored in the frame-buffer area on a display unit, pixel data at each pixel position is sequentially read for display, in synchronization with raster scanning of the display screen.
As described above, when a general data area and a frame-buffer area are both provided in an SDRAM to achieve cost reduction, the band width necessary for accessing the SDRAM increases more and more.
When being accessed in the order of address, SDRAM has an advantage in that the overhead required in the access can be reduced by the burst transfer capability. On the other hand, a disadvantage of SDRAM is that when access is made in no order of address, a precharge command and an active command have to be input to the SDRAM every time such access is made. It is thus apparent that significant overhead occurs in, e.g., display processing or processing in which a large amount of line segment data is written, if addresses and pixel data are simply associated with each other on a one-to-one basis.
A conventional technique for solving this problem will be discussed.
In the following descriptions, SDRAMs each including four banks will be exemplified as DRAMs. It is assumed that in the SDRAMs, the data line width is 32 bits and the number of column addresses per row address is 256. It is also assumed that the restriction that one cycle has to be waited between issuing active commands is imposed as command-issuing interval restriction (/RAS to /RAS bank active delay: tRRD). In the following descriptions, it is also assumed that CS (chip select signal) and CKE (clock enable signal), which are control signals for the SDRAMs, are negative logic signals.
Moreover, in the descriptions, selecting a row address in a bank included in a DRAM will be referred to as “activate a row address”. A set of control signals that is input to a DRAM to make the DRAM perform a particular operation will be referred to as a “command”. For example, a set of control signals input to a DRAM in order to activate a particular row address will be referred to as an “active command”.
FIG. 20 is a block diagram schematically illustrating the configuration of a conventional DRAM controller. FIG. 21 is a block diagram illustrating the internal configuration of an interface unit 120 of FIG. 20. In FIG. 20, the reference marks 101A, 101B, and 102 denote a first SDRAM (SDRAM1), a second SDRAM (SDRAM2), and a microprocessor for accessing the first and second SDRAMs 101A and 101B. The reference marks CS1 and CS2 indicate chip select signals, and CKE denotes a clock enable signal. The reference marks RAS, CAS, and WE denote control signals for issuing commands, while BA indicates a bank select signal.
FIG. 22 shows exemplary address mapping in a frame-buffer area in the configuration shown in FIGS. 20 and 21. In FIG. 22, a section designated by (SDRAM1, Bank0, Row2), e.g., represents a drawing block BL which has capacity for storing data indicated by a single row address. And in this case, each single row address includes 256 column addresses.
FIG. 23 illustrates the details of address mapping in a single drawing block. In the example of FIG. 23, 256 column addresses included in the single drawing block are two-dimensionally mapped in 8 columns in the horizontal direction and in 32 lines in the vertical direction. Each column address has a memory element of 32 bits. Thus, in the case of storage of drawing data including 8 bits per pixel, 4 pixels of the drawing data can be stored in each column address.
An access operation performed in the conventional configuration shown in FIGS. 20 and 21 will be described.
(1) Display processing (FIG. 24)
(Step 1)
In the interface unit 120, a CPU 201 sets, in a graphics parameter register, transfer start coordinates, a frame number, drawing data information (color depth, rectangle/line), the amount of words in horizontal width, and the number of lines in vertical width.
(Step 2)
The CPU 201 outputs to a control unit 205 a request signal that indicates transfer request.
(Step 3)
The control unit 205 first outputs to the CPU 201 an acknowledge signal for accepting the transfer request, and then refers to the graphics parameter register 203 to determine which four banks are to be activated, based on the amount of words in horizontal width and the number of lines in vertical width. In this case, (SDRAM1, Bank0, Row0), (SDRAM1, Bank1, Row0), (SDRAM1, Bank2, Row1), and (SDRAM1, Bank3, Row1) are each activated. The control unit 205 then refers to an active row address storage unit 207 to check which banks are currently active and determines whether or not a precharge command/active command has to be issued. In this case, it is assumed that the issuance is not necessary.
(Step 4)
A two-dimensional address generating unit 204 refers to the graphics parameter register 203 to calculate an address on the SDRAM, from which the writing is to be started, based on the transfer start coordinates, the frame number and the drawing data information. The two-dimensional address generating unit 204 then outputs the calculated bank Bank, row address Row, and column address Col to an address/control-signal output unit 208.
(Step 5)
The control unit 205 starts a state transition as shown in FIG. 24B for generating control signals to the SDRAM1. For example, the control unit 205 instructs the address/control-signal output unit 208 to generate an active command in a cycle T1.
(Step 6)
The address/control-signal output unit 208 first determines into which of the SDRAM1 and the SDRAM 2 the writing is to be performed, based on the row address Row output from the two-dimensional address generating unit 204. And based on the determination result, the address/control-signal output unit 208 generates chip select signals CS1 and CS2. Also, from the bank Bank and row address Row output from the two-dimensional address generating unit 204, the address/control-signal output unit 208 outputs an active command (control signals RAS, CAS, and WE) for activating (SDRAM1, Bank0, Row0).
(Step 7)
Subsequently, in accordance with the issue interval restriction tRRD, the address/control-signal output unit 208 outputs an active command for activating (SDRAM1, Bank1, Row0) in a cycle T3.
(Step 8)
At a cycle T4, which satisfies the issue interval restriction tRRD with respect to the cycle T1, it is possible to issue a read command. Therefore, a read command for (SDRAM1, Bank0, Row0) is output.
(Step 9)
Subsequently, in cycles T5 and T7, active commands for respectively activating (SDRAM1, Bank2, Row1) and (SDRAM1, Bank3, Row1) are output.
(Step 10)
In a cycle T12, a read command for (SDRAM1, Bank1, Row0) is output. Thereafter, when access moves to (SDRAM1, Bank2, Row1) and (SDRAM1, Bank3, Row1), read commands are output similarly.
(Step 11)
In cycles S1 and S3, a precharge command for (SDRAM1, Bank0) and an active command for (SDRAM1, Bank0, Row2) are respectively issued.
(Step 12)
In a cycle S5, a read command for (SDRAM1, Bank0, Row2) is issued.
As described above, the burst transfer capability of the SDRAMs permits the precharge and active commands to be issued together, while the read operation is performed. In this processing, no overhead is therefore produced when the bank boundaries are accessed.
(2) Writing of line segment data (FIG. 25)
As shown in FIG. 25, an operation for consecutively writing two line-segment data items (line segments 1 and 2) will be discussed.
In cycles T1 and T3, (SDRAM1, Bank0, Row0) and (SDRAM1, Bank3, Row0) are each activated. The activation operation is performed in the same manner as described in the display processing.
Then, in cycles T4 through T8, the line segment data of the line segment 1 is written into the drawing block (SDRAM1, Bank0, Row0). In cycles T9 through T15, the line segment data of the line segment 2 is written into the drawing block (SDRAM1, Bank3, Row0). In this case, since the column addresses into which the data items are written are not consecutive, each column address has to be output for each data item.
By the above described configuration and operations, the following effects are achieved.
(1) No overhead occurs when the frame-buffer area is read in the horizontal direction. As a result, the access time required in the display processing is reduced.
(2) Although description is omitted herein, when rectangular data of relatively large size is written, use of the SDRAMs' burst transfer capability allows pipeline access as well as a horizontal read operation, thus causing no overhead.
(3) When short line segment data and a small rectangle are written, the possibility that they are in the same row address increases. Consequently, no overhead occurs when such single drawing data is written.
In other words, the above-mentioned configuration and operations solve to some extent the conventional problem that the bandwidth increases when the frame-buffer area is accessed.
However, there still remains a problem with the conventional technique in that significant overhead may occur when DRAM is accessed in some processing, which means that the conventional technique has been insufficient to solve the above problem.
FIG. 26 illustrates an operation in which rectangles (rectangles 1 and 2), of a horizontal width of two words and having therein three lines in the vertical direction, are rendered into the frame-buffer area. As shown in FIG. 26A, the rectangle 1 extends across four drawing blocks (SDRAM1, Bank0, Row0), (SDRAM1, Bank1, Row0), (SDRAM1, Bank2, Row0), and (SDRAM1, Bank3, Row0), while the rectangle 2 extends across four drawing blocks (SDRAM1, Bank1, Row1), (SDRAM1, Bank2, Row2), (SDRAM1, Bank3, Row4), and (SDRAM1, Bank0, Row5).
As shown in FIG. 26B, writing the rectangles 1 and 2 consecutively requires as much as 24 cycles in total from T1 to T24. In this case, one reason for the occurrence of overhead is that a write command needs to be issued in succession in each cycle because the horizontal width of the rectangles is short, and a precharge command and an active command cannot be issued together with the write command.
FIG. 27 illustrates an operation in which line-segment data (line segment 3) is vertically written into the frame-buffer area. As shown in FIG. 27A, the line segment 3 extends across three drawing blocks (SDRAM1, Bank0, Row0), (SDRAM1, Bank2, Row0) and (SDRAM1, Bank0, Row3.)
As shown in FIG. 27B, cycles S3 and S5, e.g., in which no data can be written, occur. In this case, as in the case of FIG. 26, one reason for causing overhead is that a write command has to be issued in succession in each cycle, and a precharge command and an active command cannot be issued together with the write command.
As can be seen from FIG. 20, in the conventional configuration, when the plurality of SDRAMs are connected to increase the SDRAM capacity, all of the SDRAMs use in common all signal lines but a chip select signal line. Due to this, all of the SDRAMs have to be refreshed simultaneously, and during the refresh operation, no read/write operations from/into the SDRAMs can be performed. In addition, along with the trend toward increasingly greater amounts of process data, SDRAM capacity also increases correspondingly, resulting in an increase in refresh time in the SDRAM access bandwidth.
In view of the above problem, an object of the present invention is that in DRAM control in which graphics processing is performed by using DRAMs capable of burst transfers as a frame-buffer area(s), overhead is reduced to lessen the number of cycles required to access the DRAMs as compared with the conventional case, e.g., in processing which extends across a plurality of drawing blocks or in processing in which the frame-buffer areas are used.